Weslo TL5.0 Manual do Utilizador

MAGNACHIP SEMICONDUCTOR LTD.8-BIT SINGLE-CHIP MICROCONTROLLERSHMS91C8132 HMS97C8132User’s Manual (Ver. 1.6)

HMS91C8132/97C8132DEC. 2004 Ver 1.6 7operation results. )Data memory consists of 7 pages, and each page can store128bytes. According to the value of

HMS91C8132/97C8132DEC. 2004 Ver 1.6 97T2CON: TIMER/COUNTER 2 CONTROL REGISTER. BIT ADDRESSABLE. : C8HTF2 T2CON.7 Timer 2 Overflow flag set by hard

HMS91C8132/97C813298 DEC. 2004 Ver 1.6T34CON: TIMER34/COUNTER34 CONTROL REGISTER. BIT ADDRESSABLE. : 90HTF4 TCON.7 Timer 4 Overflow flag. Set by

HMS91C8132/97C8132DEC. 2004 Ver 1.6 99T5INITL / T5INITH: TIMER5 INITIALIZATION REGISTERS. NOT BIT ADDRESSABLE : 9EH,9FHThe T5INITL and T5INITH SFRs

HMS91C8132/97C8132100 DEC. 2004 Ver 1.6T34MOD: TIMER/COUNTER MODE CONTROL REGISTER. NOT BIT ADDRESSABLE. : 91HGATE T34MOD.7 When TRx (in TCON) is

HMS91C8132/97C8132DEC. 2004 Ver 1.6 101NOTES:1. The Timer is turned ON/OFF by setting/clearing bit TR0 (TR3) by the software.2. The Timer is turned

HMS91C8132/97C8132102 DEC. 2004 Ver 1.6WDTCON: BEEPER & WATCHDOG TIMER CONTROL REGISTER. BIT ADDRESSABLE. : F8HRUNBEEP WDTCON.7 Software START/

HMS91C8132/97C8132DEC. 2004 Ver 1.6 1035. INSTRUCTION SET The HMS9XC8132 instruction set is optimized for 8-bit control applications. It provides a

HMS91C8132/97C8132104 DEC. 2004 Ver 1.6Register-Specific Instructions Some instructions are specific to a certain register. For example,some instruc

HMS91C8132/97C8132DEC. 2004 Ver 1.6 105ry number to BCD. The DA A operation produces a meaningfulresult only as the second step in the addition of t

HMS91C8132/97C8132106 DEC. 2004 Ver 1.65.5 Data Transfers Internal RAM Table 5-3 shows the menu of instructions that are available formoving data ar

HMS91C8132/97C81328 DEC. 2004 Ver 1.6When the DTS_MODE bit of CPUMD SFR is set to HIGH,the internal 1K RAM can be accessed by the page schemewhich i

HMS91C8132/97C8132DEC. 2004 Ver 1.6 107First, pointers R1 and R0 are set up to point to the two bytes con-taining the last four BCD digits. Then a l

HMS91C8132/97C8132108 DEC. 2004 Ver 1.6the RET opcode itself.5.7 Boolean Instructions HMS9XC8132 devices contain a complete Boolean (single-bit)proc

HMS91C8132/97C8132DEC. 2004 Ver 1.6 109the PC in two's complement arithmetic if the jump is executed.The range of the jump is therefore -128 to

HMS91C8132/97C8132110 DEC. 2004 Ver 1.6The DJNZ instruction (Decrement and Jump if Not Zero) is forloop control. To execute a loop N times, load a c

HMS91C8132/97C8132DEC. 2004 Ver 1.6 1115.10 Instruction Set SummaryInterrupt Response Time : Refer to Hardware Description Chap-terInstructions that

HMS91C8132/97C8132112 DEC. 2004 Ver 1.6Instruction Set Summary (Continued)Mnemonic Description Byte OSC PeriodMnemonic

HMS91C8132/97C8132DEC. 2004 Ver 1.6 113Instruction Set Summary (Continued)Mnemonic Description Byte OSC PeriodMnemonic

HMS91C8132/97C8132114 DEC. 2004 Ver 1.65.11 Instruction DefinitionsACALL addr11ADD A,<src-byte>Function:Absolute CallDescription: ACALL unco

HMS91C8132/97C8132DEC. 2004 Ver 1.6 115ADD A,RnADD A,directADD A,@RiADD A,#dataBytes:1Cycles:1Encoding:0 0 1 0 1 r r rOperation: ADD(A

HMS91C8132/97C8132116 DEC. 2004 Ver 1.6ADDC A,<src-byte>ADDC A,Rn ADDC A,direct Function:Add with CarryDescription: ADDC simultaneously add

HMS91C8132/97C8132DEC. 2004 Ver 1.6 9 2.3 Special Function RegisterUnlike Intel 805X series, HMS9XC8132 has two SFR pages. Ifthe content of SFRPG (a

HMS91C8132/97C8132DEC. 2004 Ver 1.6 117ADDC A,@Ri ADDC A,#dataAJMP addr11Bytes:1Cycles:1Encoding:0 0 1 1 0 1 1 iOperation: ADDC(A) ← (

HMS91C8132/97C8132118 DEC. 2004 Ver 1.6ANL <dest-byte> , <src-byte>ANL A,RnANL A,directFunction:Logical-AND for byte variablesDescript

HMS91C8132/97C8132DEC. 2004 Ver 1.6 119ANL A,@RiANL A,#dataANL direct,AANL direct,#dataBytes:1Cycles:1Encoding:0 1 0 1 0 1 1 iOperati

HMS91C8132/97C8132120 DEC. 2004 Ver 1.6ANL C,<src-bit>ANL C,/bitFunction:Logical-AND for bit variablesDescription: If the Boolean value of t

HMS91C8132/97C8132DEC. 2004 Ver 1.6 121CJNE <dest-byte>,<src-byte>,relCJNE A,direct,relFunction:Compare and Jump if Not Equal.Descriptio

HMS91C8132/97C8132122 DEC. 2004 Ver 1.6CJNE A,#data,relCJNE Rn,#data,relBytes:3Cycles:2Encoding:1 0 1 1 0 1 0 0 immediate data rel. add

HMS91C8132/97C8132DEC. 2004 Ver 1.6 123CJNE @Ri,#data,relCLR ACLR bitBytes:3Cycles:2Encoding:1 0 1 1 0 1 1 i immediate data rel. addre

HMS91C8132/97C8132124 DEC. 2004 Ver 1.6CLR CCLR bitCPL ABytes:1Cycles:1Encoding:1 1 0 0 0 0 1 1Operation: CLR(C) ← 0Bytes:2Cycles:1En

HMS91C8132/97C8132DEC. 2004 Ver 1.6 125CPL bitCPL CCPL bitFunction:Complement bitDescription: The bit variable specified is complemented. A bit

HMS91C8132/97C8132126 DEC. 2004 Ver 1.6DA AFunction:Decimal-adjust Accumulator for AdditionDescription: DA A adjusts the eight-bit value in the Acc

HMS91C8132/97C813210 DEC. 2004 Ver 1.63. HARDWARE DESCRIPTION This chapter provides a detailed description of the HMS9XC8132 microcontroller (see Fi

HMS91C8132/97C8132DEC. 2004 Ver 1.6 127DEC byteDEC ADEC directFunction:DecrementDescription: The variable indicated is decremented by 1. An origi

HMS91C8132/97C8132128 DEC. 2004 Ver 1.6DEC @RiDIV ABBytes:1Cycles:1Encoding:0 0 0 1 0 1 1 i rOperation: DEC((Ri)) ← ((Ri)) - 1Functi

HMS91C8132/97C8132DEC. 2004 Ver 1.6 129DJNZ <byte>,<rel-addr>DJNZ Rn,relFunction:Decrement and Jump if Not ZeroDescription: DJNZ decre

HMS91C8132/97C8132130 DEC. 2004 Ver 1.6DJNZ direct,relINC <byte>INC AINC RnBytes:3Cycles:2Encoding:1 1 0 1 0 1 0 1 direct addr

HMS91C8132/97C8132DEC. 2004 Ver 1.6 131INC directINC @RiINC DPTRBytes:2Cycles:1Encoding:0 0 0 0 0 1 0 1 direct addressOperation: INC(

HMS91C8132/97C8132132 DEC. 2004 Ver 1.6JB bit,relJBC bit,relFunction:Jump if Bit setDescription: If the indicated bit is a one, jump to the addre

HMS91C8132/97C8132DEC. 2004 Ver 1.6 133JC relJMP @A + DPTRFunction:Jump if Carry is setDescription: If the carry flag is set, branch to the addre

HMS91C8132/97C8132134 DEC. 2004 Ver 1.6JNB bit,relJNC relFunction:Jump if Bit Not setDescription: If the indicated bit is a zero, branch to the in

HMS91C8132/97C8132DEC. 2004 Ver 1.6 135JNZ relJZ relFunction:Jump if Accumulator Not ZeroDescription: If any bit of the Accumulator is a one, bran

HMS91C8132/97C8132136 DEC. 2004 Ver 1.6LCALL addr16LJMP addr16Function:Long callDescription: LCALL calls a subroutine located at the indicated add

HMS91C8132/97C8132DEC. 2004 Ver 1.6 113.1 Clock Generation BlockSoftware can control the system clock speed of HMS91C8132with the SCMOD register. t

HMS91C8132/97C8132DEC. 2004 Ver 1.6 137MOV <dest-byte>,<src-byte>MOV A,Rn*MOV A,directMOV A, ACC is not a vaild instruction.Function

HMS91C8132/97C8132138 DEC. 2004 Ver 1.6MOV A,@RiMOV A,#dataMOV Rn,AMOV Rn,directBytes:1Cycles:1Encoding:1 1 1 0 0 1 1 iOperation: MO

HMS91C8132/97C8132DEC. 2004 Ver 1.6 139MOV Rn,#daraMOV direct,AMOV direct,RnMOV direct,directMOV direct,@RiBytes:2Cycles:1Encoding:0 1 1

HMS91C8132/97C8132140 DEC. 2004 Ver 1.6MOV direct,#dataMOV <dest-bit>,<src-bit>MOV C,bitMOV bit,CBytes:3Cycles:2Encoding:0 1 1

HMS91C8132/97C8132DEC. 2004 Ver 1.6 141MOV DPTR,#data16MOVC A,@A + <base-reg>Function:Load Data Pointer with a 16-bit constantDescription: T

HMS91C8132/97C8132142 DEC. 2004 Ver 1.6MOVC A,@A + DPTR MOVC A,@A + PCMOVX A,@RiMOVX A,@DPTRMOV @Ri,ABytes:1Cycles:2Encoding:1 0 0 1 0 0

HMS91C8132/97C8132DEC. 2004 Ver 1.6 143MOVX @DPTR,AMUL ABOperation: MOVX((Ri)) ← (A)Bytes:1Cycles:2Encoding:1 1 1 1 0 0 0 0Operation:

HMS91C8132/97C8132144 DEC. 2004 Ver 1.6NOPORL <dest-byte>,<src-byte>Function:No OperationDescription:Execution continues at the followi

HMS91C8132/97C8132DEC. 2004 Ver 1.6 145ORL A,RnORL A,directORL A,@RiORL A,#dataORL direct,ABytes:1Cycles:1Encoding:0 1 0 0 1 r r rO

HMS91C8132/97C8132146 DEC. 2004 Ver 1.6ORL direct,#dataORL C,<src-bit>ORL C,bitORL C,/bitBytes:3Cycles:2Encoding:0 1 0 0 0 0 1

HMS91C8132/97C813212 DEC. 2004 Ver 1.63.2 Machine Cycles A machine cycle consists of a sequence of 6 states, numbered S1through S6. One machine cycl

HMS91C8132/97C8132DEC. 2004 Ver 1.6 147POP directPUSH directFunction:Pop from stack.Description: The contents of the internal RAM location address

HMS91C8132/97C8132148 DEC. 2004 Ver 1.6RETRETIFunction:Return from subroutineDescription: RET pops the high- and low-order bytes of the PC successi

HMS91C8132/97C8132DEC. 2004 Ver 1.6 149RL ARLC AFunction:Rotate Accumulator LeftDescription: The eight bits in the Accumulator are rotated one bit

HMS91C8132/97C8132150 DEC. 2004 Ver 1.6RR ARRC AFunction:Rotate Accumulator RightDescription: The eight bits in the Accumulator are rotated one bi

HMS91C8132/97C8132DEC. 2004 Ver 1.6 151SETB <bit>SETB bitFunction:Set BitDescription: SETB sets the indicated bit to one. SETB can operate

HMS91C8132/97C8132152 DEC. 2004 Ver 1.6SJMP relSUBB A,<src-byte>4Function:Short JumpDescription: Program control branches unconditionally to

HMS91C8132/97C8132DEC. 2004 Ver 1.6 153SUBB A,RnSUBB A,directSUBB A,@RiSUBB A,#dataBytes:1Cycles:1Encoding:1 0 0 1 1 r r rOperation:

HMS91C8132/97C8132154 DEC. 2004 Ver 1.6SWAP AXCH A,<byte>XCH A,RnFunction:Swap nibbles within the AccumulatorDescription: SWAP A interchang

HMS91C8132/97C8132DEC. 2004 Ver 1.6 155XCH A,directXCH A,@RiXCHD A,@RiBytes:2Cycles:1Encoding:1 1 0 0 0 1 0 1 direct addressOperation

HMS91C8132/97C8132156 DEC. 2004 Ver 1.6XRL <dest-byte>,<src-byte>XRL A,RnXRL A,directFunction:Logical Exclusive-OR for byte variables

HMS91C8132/97C8132DEC. 2004 Ver 1.6 133.3 Timer/Counters (Timer0, Timer1 and Timer2) The HMS9XC8132 has five 16-bit Timer/Counter registers: Tim-er

HMS91C8132/97C8132DEC. 2004 Ver 1.6 157XRL A,@RiXRL A,#dataXRL direct,AXRL direct,#dataBytes:1Cycles:1Encoding:0 1 1 0 0 1 1 iOperat

HMS91C8132/97C8132158 DEC. 2004 Ver 1.66. ELECTRICAL CHARACTERISTICS6.1 Absolute Maximum RatingsPower Supply voltage...

HMS91C8132/97C8132DEC. 2004 Ver 1.6 159INTERRUPT TIMING WAVEFORMRESET TIMING WAVEFORMTIMER INPUT TIMING WAVEFORMTINTLnINT0 to INT6TINTHnTRSLRESETTTL

HMS91C8132/97C8132160 DEC. 2004 Ver 1.6SERIAL INTERFACE(SIO) (TA = -40° to +85°, VDD = 3.0 to 5.5 V)• 3-wire serial I/O mode (SCK0 … internal cloc

HMS91C8132/97C8132DEC. 2004 Ver 1.6 161SERIAL PORT(UART) TIMING Test Conditions : Over Operation Conditions ; Load Capacitance = 80 pF * Note. Whe

HMS91C8132/97C8132162 DEC. 2004 Ver 1.6PLL CHARACTERISTIC (TA = -40° to +85°, VDD = 4.5 to 5.5 V)IFC CHARACTERISTIC (TA = -40° to +85°, VDD = 4.5

HMS91C8132/97C8132DEC. 2004 Ver 1.6 1636.4 DC CharacteristicsPower Specification (HMS 91C8132) (TA = -40° to +85°, VDD = 5.0 V)Power Specification

HMS91C8132/97C8132164 DEC. 2004 Ver 1.6Port Type 2 (P7)Port Type 3 (P3.0 – P3.4, P4.0 – P4.6, P5.0, P5.1, P5.2, P5.4, P5.5, P5.7, RESET)Parameter Sy

HMS91C8132/97C8132DEC. 2004 Ver 1.6 165Port Type 4 (P2.0 – P2.3, Open Drain)Parameter Symbol Test Condition Min. Typ. Max. UnitInput Voltage HighVIH

HMS91C8132/97C8132166 DEC. 2004 Ver 1.66.5 CPU Timing All HMS9XC8132 microcontrollers have an on-chip oscillatorwhich can be used if desired as the

HMS91C8132/97C813214 DEC. 2004 Ver 1.6Mode 2 Mode 2 configures the Timer register as an 8-bit Counter (TL1)with automatic reload, as shown in Figure

HMS91C8132/97C8132DEC. 2004 Ver 1.6 1677. EPROM CHARACTERISTICSThe HMS97C8132 has internal 32K bytes OTP ROM. The HMS97C8132 is programmed with a mo

HMS91C8132/97C8132168 DEC. 2004 Ver 1.67.3 Program VerificationIf lock bit 2 (LB2 in Table 7-1) has not been programmed, theon-chip program memory c

HMS91C8132/97C8132DEC. 2004 Ver 1.6 169Notes:“0” = Valid low for that pin, “1” = Valid high for that pin.VPP = 11.5V ± 0.25VVCC = 5V ± 10% during pr

HMS91C8132/97C8132170 DEC. 2004 Ver 1.6TA=21°C to 27°C; VCC= 5V±10%; VSS=0VFigure 7-4 EPROM Programming and VerificationFigure 7-5 Two Consecutive R

HMS91C8132/97C8132DEC. 2004 Ver 1.6 171 Parameter Symbol Min Max UnitsProgramming Supply VoltageVPP11.3 11.7 VProgramming Supply CurrentIPP75 mAOsci

HMS91C8132/97C8132172 DEC. 2004 Ver 1.6Figure 7-7 Program AlgorithmN=0Set VDD=5.0VN=N+1First AddressN=1Set VPP=11.5VVerify BlankVerify PassLast Addr

HMS91C8132/97C8132DEC. 2004 Ver 1.6 1738. OTP PROGRAMMING8.1 HMS97C8132 OTP ProgrammingBlank CheckSince the initial values of program memory and enc

HMS91C8132/97C8132174 DEC. 2004 Ver 1.6Intel87C58 (ADAPTER) HMS97C8132P1.0(A0) 1 P0.0(A0) 1P1.1(A1) 2 P0.1(A1) 2P1.2(A2) 3 P0.2(A2) 3P1.3(A3) 4 P0.3

HMS91C8132/97C8132DEC. 2004 Ver 1.6 1759. DEVELOPMENT TOOLSThe HMS97C8132 and HMS91C8132 are supported by a macroassembler, an in-circuit emulator i

HMS91C8132/97C8132176 DEC. 2004 Ver 1.69.1 HMS91C8132 Emulator POD ConnectorFigure 9-3 HMS91C8132 Emulator PODHMS91C8032(HMS91C8132)Emulator PODBot

HMS91C8132/97C8132DEC. 2004 Ver 1.6 15Timer 2 In addition to timer/counter 0, 1, 3 and 4 of the HMS9XC8132,the HMS9XC8132 contains timer/counter 2.

HMS91C8132/97C8132DEC. 2004 Ver 1.6 17710. PACKAGE DIMENSION80MQFPUNIT : mm18023.90±0.2520.00±0.1017.90±0.2514.00±0.1014.00±0.100.37±0.080.80 PITCH0

HMS91C8132/97C8132178 DEC. 2004 Ver 1.611. MASK ORDER SHEETMASK ORDER & VERIFICATION SHEETHMS91C81 -DB1. Customer InformationCompany Name

HMS91C8132/97C813216 DEC. 2004 Ver 1.6Timer/Counter 2 Set-up T2CON do not include the setting of the TR2 bit. Therefore, bitTR2 must be set, separat

Version 1.6Published byMCU Team2001 MagnaChip Semiconductor Inc. All right reserved.Additional information of this manual may be served by MagnaChip

HMS91C8132/97C8132DEC. 2004 Ver 1.6 173.4 Timer/Counters (Timer3 and Timer4)HMS9XC8132 has five 16-bit general-purpose Timer/Counter.Timer0, Timer1

HMS91C8132/97C813218 DEC. 2004 Ver 1.6Figure 3-12 Clock Counting Sources fot Timer3/Counter3 and Timer4/Counter4Figure 3-13 T34CON RegisterXin / 12X

HMS91C8132/97C8132DEC. 2004 Ver 1.6 193.5 Timer 5HMS9XC8132 has the additional 16-bits counter named astimer5. It can count the number of clock cycl

HMS91C8132/97C813220 DEC. 2004 Ver 1.6T5CON: TIMER5 CONTROL REGISTER. NOT BIT ADDRESSABLE : 9DHT5EN T5CON.7 Timer 5 enable flag. When this flag is

HMS91C8132/97C8132DEC. 2004 Ver 1.6 213.6 Standard Serial Interface (UART) The serial port is full duplex, meaning it can transmit and receivesimult

HMS91C8132/97C813222 DEC. 2004 Ver 1.6* fCPU : CPU clock* The fCPU is shown in Figure 3-2Baud Rates The baud rate in Mode 0 is fixed:The baud rate

HMS91C8132/97C8132DEC. 2004 Ver 1.6 23ation. In the most typical applications, it is configured for “timer”operation (C/T2 = 0). “Timer” operation

HMS91C8132/97C813224 DEC. 2004 Ver 1.6at the 10th divide-by-16 rollover after "write to SBUF."Reception is initiated by a detected 1-to-0

HMS91C8132/97C8132DEC. 2004 Ver 1.6 25Figure 3-18 Serial Port Mode 0D0Write to SBUFS6P2ShiftRxD (Data Out)D1 D2 D3 D4 D5 D6 D7TITransmitRISBUFZero

HMS91C8132/97C813226 DEC. 2004 Ver 1.6Figure 3-19 Serial Port Mode 1SBUFZero DetectorInternal BusDSQCL16WritetoSBUFSMOD = 0SMOD = 1SerialPortInterr

HMS91C8132/97C8132SEP. 2004 Ver 1.6Table of Contents1. OVERVIEW...1Description ...

HMS91C8132/97C8132DEC. 2004 Ver 1.6 27Figure 3-20 Serial Port Mode 2.SBUFZero DetectorInternal BusDSQCL16WritetoSBUF2SMOD = 0(SMOD isPCON.7)SMOD = 1

HMS91C8132/97C813228 DEC. 2004 Ver 1.6Figure 3-21 Serial Port Mode 3SBUFZero DetectorInternal BusDSQCL16WritetoSBUFSMOD = 0SMOD = 1SerialPortInterr

HMS91C8132/97C8132DEC. 2004 Ver 1.6 293.7 Standard Serial Interface (SIO 1, SIO 2) Configuration of Serial Interface Figure 3-22 shows the block dia

HMS91C8132/97C813230 DEC. 2004 Ver 1.6Outline of function of serial interfaceThe SIO1 and SIO2 permits use of 3-wire serial I/O system. TheSIO1 and

HMS91C8132/97C8132DEC. 2004 Ver 1.6 31Setting of Each pin by serial I/O mode select reg-isterThe setting of each pin also requires handling of the i

HMS91C8132/97C813232 DEC. 2004 Ver 1.6 (a) Ordinary wait with clock counter reached “8” (b)Forced wait during a wait (c) Forced wait dur

HMS91C8132/97C8132DEC. 2004 Ver 1.6 33initial value of the clock counter is 0, and counter value incre-ments (+1) upon each detection of the falling

HMS91C8132/97C813234 DEC. 2004 Ver 1.6Operation of Serial bufferThe operation is shown below.Data shift operation of Serial bufferPrecautions in Dat

HMS91C8132/97C8132DEC. 2004 Ver 1.6 35SIO2TS flag turning to 0. This means that correct data setting andreading may fail if data setting or data rea

HMS91C8132/97C813236 DEC. 2004 Ver 1.6Figure 3-27 Input/Ouitput Block of the SIO and Communication Methodd7d6 d5 d1 d0123 78Wait cancelShift ClockS

HMS91C8132/97C8132DEC. 2004 Ver 1.6 1HMS91C8132HMS97C81321. OVERVIEW1.1 DescriptionThe HMS91C8132 and the HMS97C8132 are a member of the HMS9XC8132

HMS91C8132/97C8132DEC. 2004 Ver 1.6 37Figure 3-28 Operation of Each Mode of the SIOOutputSIO1/SIO2TSWRITEPortRegisterREADLatchSCK1/2OutputWRITEPortR

HMS91C8132/97C813238 DEC. 2004 Ver 1.63.8 Port Structure and OperationPorts 0 to 7The direction of each port is controlled by the value of PXMODregi

HMS91C8132/97C8132DEC. 2004 Ver 1.6 39In the execution of an instruction that changes the value in a portlatch, the new value arrives at the latch d

HMS91C8132/97C813240 DEC. 2004 Ver 1.63.9 Watch Dog TimerWatchdog Timer FunctionsThe watchdog timer has the following functions.• Non-maskable watch

HMS91C8132/97C8132DEC. 2004 Ver 1.6 41timer interrupt(Maskable Interrupt or Non Maskable Interrupt)are selected by WDTMK flag. If maskable interrupt

HMS91C8132/97C813242 DEC. 2004 Ver 1.63.10 BuzzerBuzzer Output Control Circuit FunctionsThe buzzer output control circuit outputs 1.2KHz, 2.4KHz,4.5

HMS91C8132/97C8132DEC. 2004 Ver 1.6 433.11 IF CounterFunction of Frequency CounterThe frequency counter counts the intermediate frequency (IF) ofa t

HMS91C8132/97C813244 DEC. 2004 Ver 1.6IFCMOD: IF counter mode register. : F4H * Software controls IFC gate time. IF counts during IFCST flag is high

HMS91C8132/97C8132DEC. 2004 Ver 1.6 45IF Counter Data RegisterIF counter data registers (IFCDR2, IFCDR1 and IFCDR0) are read only registers. Attempt

HMS91C8132/97C813246 DEC. 2004 Ver 1.6The relationship between count value N (decimal), input frequen-cies, and gate time is shown below. (1) FM

HMS91C8132/97C81322 DEC. 2004 Ver 1.61.3 FeaturesItem FeaturesROM 32K x 8-bitRAM 1K x 8-bitInstruction CycleWith variable instruction execution time

HMS91C8132/97C8132DEC. 2004 Ver 1.6 47Notes on Frequency Counter(1) Notes on using frequency counterBecause signals are input to the frequency count

HMS91C8132/97C813248 DEC. 2004 Ver 1.6. (2) Error of frequency counterError of gate timeThe gate time of the frequency counter is created by dividin

HMS91C8132/97C8132DEC. 2004 Ver 1.6 493.12 PLLThe phase locked loop (PLL) frequency synthesizer is used tolock medium frequency (MF), high frequency

HMS91C8132/97C813250 DEC. 2004 Ver 1.6reference frequencies (1, 1.25, 2.5, 3, 5, 6.25, 9, 10, 12.5, 25,50KHz) can be selected using a PLL reference

HMS91C8132/97C8132DEC. 2004 Ver 1.6 51PLLMOD : PLL Mode Register. : F1H * User software should not write 1s to reserved bits. These bitsmay be use

HMS91C8132/97C813252 DEC. 2004 Ver 1.6Programmable Divider and PLL Data RegisterThe programmable divider divides the frequency of a signal fromthe V

HMS91C8132/97C8132DEC. 2004 Ver 1.6 53Phase Comparator FunctionsAs shown in Figure 3-41, the comparator compares the phase offrequency division outp

HMS91C8132/97C813254 DEC. 2004 Ver 1.6(1) Frequency division system : Direct frequency division (MF)and pulse swallow (HF and VHF)(2) Pin used : VCO

HMS91C8132/97C8132DEC. 2004 Ver 1.6 55Receive frequency : 1260KHz (MW band)Reference frequency : 9KHzIntermediate frequency : +450KHzFrequency divis

HMS91C8132/97C813256 DEC. 2004 Ver 1.63.13 ADCThe analog-to-digital converter (A/D) allows conversion of ananalog input signal to a corresponding 8-

HMS91C8132/97C8132DEC. 2004 Ver 1.6 31.4 Pin DescriptionPinNamesPortNamesAlternatives Functions Reset12345678P0.0P0.1P0.2P0.3P0.4P0.5P0.6P0.78-bit g

HMS91C8132/97C8132DEC. 2004 Ver 1.6 57Guideline on ADCProgrammers who want to use ADC in HMS91C8132 seriesshould follow the recommended rules.1. To

HMS91C8132/97C813258 DEC. 2004 Ver 1.63.14 Interrupts The HMS9XC8132 provides 18 interrupt sources. (The 7 externalinterrupts and 11 internal interr

HMS91C8132/97C8132DEC. 2004 Ver 1.6 592. The current (polling) cycle is not the final cycle in the execu-tion of the instruction in progress.3. Th

HMS91C8132/97C813260 DEC. 2004 Ver 1.6to S5P2 of the machine cycle labeled C3 in Figure 20, then in ac-cordance with the above rules it will be vect

HMS91C8132/97C8132DEC. 2004 Ver 1.6 61JB P3.2,$ ; Wait Till Goes LowRETI ; Go Back and Execute One Instruction Now if the pin is held norm

HMS91C8132/97C813262 DEC. 2004 Ver 1.63.15 Reset The reset input is the RST pin, which is the input to a SchmittTrigger. A reset is accomplished by

HMS91C8132/97C8132DEC. 2004 Ver 1.6 633.17 Power failure detection logicHMS9XC8132 has the power failure detection logic which iscontrolled by PFDCR

HMS91C8132/97C813264 DEC. 2004 Ver 1.63.18 Power-Saving Modes of Operation For applications where power consumption is critical the CMOSversion prov

HMS91C8132/97C8132DEC. 2004 Ver 1.6 653.19 The On-Chip Oscillators The on-chip oscillator circuitry for the HMS9XC8132, shown inFigure 3-51, consist

HMS91C8132/97C813266 DEC. 2004 Ver 1.6Main Clock 7.2 MHz Oscillator : Xout, Xin C1 = C2 = 30pF ° ± 10pFSub Clock 32.768 KHz Oscillator : XT

HMS91C8132/97C81324 DEC. 2004 Ver 1.64142434445464748P5.0P5.1P5.2P5.3P5.4P5.5P5.6P5.7TxDRxDSCK1SO1SI1SCK2SO2SI28-bit general purpose bidirectional P

HMS91C8132/97C8132DEC. 2004 Ver 1.6 673.20 Power Line Configuration Power line of the HMS91C8132 are separated the I/OPAD, the CORE and the PLL.Figu

HMS91C8132/97C813268 DEC. 2004 Ver 1.6.Figure 3-55 Schematic of Power Line TSTENVSS3VDD3VDD(Digital) : VDD1, VDD231081412161524151311967201824222321

HMS91C8132/97C8132DEC. 2004 Ver 1.6 694. SPECIAL FUNCTION REGISTERSA map of the on-chip memory area called the Special FunctionRegister (SFR) space

HMS91C8132/97C813270 DEC. 2004 Ver 1.6AccumulatorACC is the Accumulator register. The mnemonics for accumula-tor-specific instructions, however, ref

HMS91C8132/97C8132DEC. 2004 Ver 1.6 714.2 Reset Value of the SFRs* com(Common) : The com can both SFR Page0 and SFR Page1Address Symbol Register D

HMS91C8132/97C813272 DEC. 2004 Ver 1.6Reset Value of SFR* com(Common) : The com can both SFR Page0 and SFR Page1Address Symbol Register Descriptio

HMS91C8132/97C8132DEC. 2004 Ver 1.6 73Reset Value of SFR* com(Common) : The com can both SFR Page0 and SFR Page1Address Symbol Register Descriptio

HMS91C8132/97C813274 DEC. 2004 Ver 1.6Reset Value of SFR* com(Common) : The com can both SFR Page0 and SFR Page1Address Symbol Register Descriptio

HMS91C8132/97C8132DEC. 2004 Ver 1.6 754.3 Summary of SFRADCCON: ADC CONTROL REGISTER. BIT ADDRESSABLE. : 84H - ADCCON.7 Reserved for future use *A

HMS91C8132/97C813276 DEC. 2004 Ver 1.6Vr means that when schmit trigger buffer output is LOW, input voltage above it makes the output of schmit trig

HMS91C8132/97C8132DEC. 2004 Ver 1.6 51.5 Pin Diagram Figure 1-1 HMS9XC8132 Pin Diagram123456789101112131415161718192021222324P0.0P0.1P0.2P0.3P0.4P0.

HMS91C8132/97C8132DEC. 2004 Ver 1.6 77AMPLNC: AM PLL LOW NOISE CONFIGURATION. NOT BIT ADDRESSABLE : EDHAMPLNC SFR is used to remove noise on the VC

HMS91C8132/97C813278 DEC. 2004 Ver 1.6CPUMD: CPU MODE REGISTER. NOT BIT ADDRESSABLE : D7HThe CPUMD SFR determines the power detection level, interna

HMS91C8132/97C8132DEC. 2004 Ver 1.6 79FMPNC: FM PLL NOISE CONFIGURATION REGISTER. NOT BIT ADDRESSABLE : EFHFMPNC SFR is used to remove noise on the

HMS91C8132/97C813280 DEC. 2004 Ver 1.63. Begin the interrupt service routine at the corresponding Vector Address of that interrupt. See Table below

HMS91C8132/97C8132DEC. 2004 Ver 1.6 81IE3: INTERRUPT ENABLE REGISTER 3. BIT ADDRESSABLE. : C0HIf the bit is 0, the corresponding interrupt is disab

HMS91C8132/97C813282 DEC. 2004 Ver 1.6IFCDR0 : IF counter data register 0. : F7HIFCMOD : IFC MODE SELECT & CONTROL REGISTER. BIT ADDRESSABLE.

HMS91C8132/97C8132DEC. 2004 Ver 1.6 83IP: INTERRUPT PRIORITY REGISTER. BIT ADDRESSABLE. : B8HIf the bit is 0, the corresponding interrupt has a low

HMS91C8132/97C813284 DEC. 2004 Ver 1.6IP2: INTERRUPT PRIORITY REGISTER 2. : B1HIf the bit is 0, the corresponding interrupt has a lower priority and

HMS91C8132/97C8132DEC. 2004 Ver 1.6 85IR3: INTERRUPT REQUEST REGISTER 3. BIT ADDRESSABLE. : E8H - IR3.7 Reserved for future use *IRWDT IR3.6 Watch

HMS91C8132/97C813286 DEC. 2004 Ver 1.6PCON: POWER CONTROL REGISTER. NOT BIT ADDRESSABLE. : 87HSMOD PCON.7 Double baud rate bit. If Timer 1 is used

HMS91C8132/97C81326 DEC. 2004 Ver 1.62. MEMORY ORGANIZATIONAll HMS91C8132 devices have separate address spaces for pro-gram and data memory. The log

HMS91C8132/97C8132DEC. 2004 Ver 1.6 87P2CON: PORT2 CON REGISTER. NOT BIT ADDRESSABLE. : A6HP2CON7 P2CON.7 Software Enable/Disable pull-up TR contro

HMS91C8132/97C813288 DEC. 2004 Ver 1.6P6CON: PORT6 CON REGISTER. NOT BIT ADDRESSABLE. : AEHP6CON7 P6CON.7 Software Enable/Disable pull-up TR contro

HMS91C8132/97C8132DEC. 2004 Ver 1.6 89P2MOD: PORT2 MODE REGISTER. NOT BIT ADDRESSABLE. : B6HP2MD7 P2MOD.7 Software Input/Output mode control flag f

HMS91C8132/97C813290 DEC. 2004 Ver 1.6P6MOD: PORT6 MODE REGISTER. NOT BIT ADDRESSABLE. : BEHP6MD7 P6MOD.7 Software Input/Output mode control flag f

HMS91C8132/97C8132DEC. 2004 Ver 1.6 91PLLMOD : PLL MODE & REFERENCE FREQUENCY SELECT REGISTER. BIT ADDRESSABLE. : F1HPLLRF3 PLLMOD.7 See Table

HMS91C8132/97C813292 DEC. 2004 Ver 1.6PSLOPE: PORT SLOPE CONTROL REGISTER. NOT BIT ADDRESSABLE : C7HThe PSLOPE SFR determines the slope of output p

HMS91C8132/97C8132DEC. 2004 Ver 1.6 93SCMOD : SYSTEM CLOCK & POWER CONTROL REGISTER. BIT ADDRESSABLE. : 80H - SCMOD.7 Reserved for future use

HMS91C8132/97C813294 DEC. 2004 Ver 1.6* fCPU : CPU Clock Frequency (fOSC/2, fOSC/4, fOSC/8, fOSC/16, fOSC/32) fOSC : Oscillator Clock FrequencySER

HMS91C8132/97C8132DEC. 2004 Ver 1.6 95For this purpose, Timer 2 must be used in the baud rate generating mode. If Timer 2 is being clocked through p

HMS91C8132/97C813296 DEC. 2004 Ver 1.6S12CON: SIO1 & SIO2 CONTROL REGISTER. BIT ADDRESSABLE. : A0HSIO2HIZ S12CON.7 Software Port control for Si